1. Technical Field
The present invention relates in general to electronic circuitry and in particular to clock generation circuitry. Still more particularly, the present invention relates to a method and system for detecting transient clock synthesis faults in phase-locked loop (PLL) clock generators.
2. Description of the Related Art
Highly integrated digital systems (e.g., computers) are currently migrating toward the use of a single system-wide reference clock from which all other clock signals are synthesized. The primary rationale for this approach has been to reduce the number of discrete crystal oscillators used in the system and to achieve clock synchronization between digital circuits within the system. In current systems, all of the derivative clock signals are synthesized from the reference clock signal utilizing phase-locked loop (PLL) clock generators.
A conventional PLL clock generator includes two basic components—a phase detector and an oscillator—that are connected in a closed-loop feedback configuration. The phase detector receives the reference clock signal and the derivative clock signal produced by the oscillator as inputs and outputs an error signal indicative of a phase difference between the two. This error signal is utilized to continuously adjust the phase and frequency of the derivative clock signal so that it tracks the reference clock signal. While the derivative clock signal may have the same or different frequency than the reference clock signal, the derivative and reference clock signals are intended to have a fixed phase relationship.
While conventional PLL clock generators are robust and are capable of maintaining lock (i.e., a fixed phase relationship between the reference clock signal and the derivative clock signal) for weeks or months of continuous operation, PLL clock generators are susceptible to transient errors and will occasionally loose lock with the reference clock signal. The probability that a PLL will loose lock is determined by the signal-to-noise ratio of the PLL inputs. Thus, if a noise spike occurs at a PLL input, the phase detector of the PLL will output an erroneous error signal, which will in turn cause the PLL oscillator to overcorrect. When this phenomenon occurs, the PLL momentarily looses lock and then regains lock usually within a single cycle of the reference clock signal.
This “cycle slip,” while typically causing only a change in the phase relationship between the reference clock signal and the derivative clock signal, alters the clock-data timing relationship and therefore corrupts the data transmitted in synchronization with the derivative clock signal. In some environments, such as digital wireless communication, such data corruption is only a minor annoyance that results in the loss of one or more (typically non-critical) data packets. However, in complex digital systems such as multiprocessor computer systems, the data corruption resulting from PLL clock generation errors can be catastrophic, with errors cascading throughout the system.